One or more embodiments relate to the operation of a nonvolatile memory device and, more particularly, to a nonvolatile memory device and a method of operating the same, which are capable of improving the reliability of data by reducing errors occurring when data is read.
A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer unit, etc. The memory cell array includes a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a plurality of cell strings corresponding to the respective bit lines.
The row decoder, coupled to a string selection line, word lines, and a common source line, is placed on one side of the memory cell array. The page buffer unit coupled to the plurality of bit lines is placed on the other side of the memory cell array.
Recently, to further increase the degree of integration of flash memory cells, active research is being done on a multi-bit cell which is able to store plural data in a single memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing a single bit is called a single level cell (SLC).
FIG. 1 is a flowchart illustrating a data read operation of a nonvolatile memory device.
Referring to FIG. 1, the nonvolatile memory device reads data using a previously set read voltage in response to a read command at step S101.
Data bits having errors as a result of reading data using the read voltage are corrected by an error correction code (ECC) operation at step S103. Next, corrected data is outputted at step S105. To this end, the nonvolatile memory device stores an error detection code (EDC) for checking whether an error has occurred when storing data.
If the number of data bits having errors is a predetermined number or less, the ECC operation can be performed on the data bits. However, if the number of data bits having errors is too many to the extent that the ECC operation cannot be performed on the data bits, the nonvolatile memory device lowers a read voltage and performs a data read operation again using the lowered read voltage in order to reduce the number of data bits with errors.
As a nonvolatile memory device repeatedly performs program and erase operations, a distribution of the threshold voltages of memory cells is widened. Accordingly, if a data read voltage is lowered, memory cells with errors can be reduced. If the number of memory cells with errors is reduced, an ECC operation can be performed.
In the case where data is read from a first memory cell, determined to have an error when data was first read from the first memory cell, using a lowered read voltage, there is no way of determining whether data actually stored in the first memory cell was ‘0’ or ‘1’.
That is, there is no method of determining whether the data stored in the first memory cell has been read as being ‘0’ because data ‘1’ (i.e., an erase state) was originally stored in the first memory cell, and the threshold voltage of the first memory cell greatly shifted higher, or whether the data stored in the first memory cell has been read as being ‘1’ because data ‘0’ (i.e., a program state) was originally stored in the first memory cell, and the threshold voltage of the first memory cell greatly dropped. Accordingly, there is concern regarding the reliability of error correction.
Furthermore, an ECC circuit is problematic in that it occupies a wide area when newly configuring a nonvolatile memory device.